1. Field of the Invention
The present invention relates generally to charge pumps, and more particularly, to charge pumps used in phase locked loops.
2. Background Art
Phase locking was invented in the 1930s, and is widely used in the electronics and communication systems. A Phase Locked Loop (PLL) can be used to synthesize new clocks by multiplication from input frequency. A PLL can also be used to suppress fast jitter, or to reduce timing skew between data and clock.
In recent years, with the development of VLSI technologies, PLLs have finally been integrated on a chip without external components. This significantly reduces their cost, and enables more applications with enhanced performance and more features.
For PLLs, jitter is an important parameter. It is observed at the crossing point of the clock waveform. Jitter is the time difference by which the PLL deviates from an ideal crossing point. Low-jitter PLLs are especially important in high-speed digital communication chips, where timing of the data transfer is critical.
FIG. 1 illustrates a conventional tri-state charge pump, coupled to receive differential UP and DOWN signals from a phase detector (not shown). The charge pump is implemented as two switched current sources 30 and 32 driving a capacitor 34. FET switches 36, 38, 40, 42 and an operational transconductance amplifier (OTA) 39 are connected as shown, driven by differential UP/DOWN signals. An output voltage Vc controls the oscillation frequency of a voltage controlled oscillator (VCO) of the PLL. The UP/DOWN signals represent feedback to either increase or decrease the VCO frequency by either charging or discharding the capacitor 34.
Although a transistor operating in the saturation region has good output impedance, it is not infinite. The current sources 30, 32 with finite output impedances are not desirable. The result is that the charge up and down current depends on the output voltage Vc. This relationship can be approximated by delta(Ids)=delta(Vds)/ROUT, where delta(Vds) is the small change at the drain-to-source voltage of a transistor, delta(Ids) is the drain current change due to the Vds drop, and ROUT is the output impedance. The output impedance ROUT can be in the range of a few megaohms, and it is significantly lower when the drain to source voltage (Vds) is low, where the transistor is close to a triode region.
For a charge pump to have a linear response, the charge up and down control signals (UP/DOWN) need to overlap for a short period of time to avoid a ‘dead zone’. Otherwise, the charge pump would have a non-linear response when the PLL is near the lock condition. The charge is given by the current multiplied by time: dQ=(IUP*TUP−IDOWN*TDOWN). If IUP=IDOWN, dQ=IUP*(TUP−TDOWN). By the overlapping the time, the dead zone problem is solved. Ideally TUP=TDOWN, thus dQ=IUP*(TUP−TDOWN)=0. That means there is no net charge delivered to the output node (Vc).
The charge pump is thus an important component in a charge pump PLL. The output of the charge pump usually directly controls the VCO. Therefore, any non-idealities in the charge pump due to IUP/IDOWN imbalance result in jitter in the PLL.
One of these non-idealities is DC offset, which occurs when the charge pump has unbalanced up and down currents IUP/IDOWN. Due to the unbalance, the charge injected to the output is given by the equation: dQ=(IUP*TUP−IDOWN*TDOWN). When TUP=TDOWN, dQ=(IUP−IDOWN)*TUP, which is not zero, since IUP is not equal to IDOWN. That means there is net charge delivered to the output node Vc.
With this DC offset, a PLL will still lock, but there is a phase difference between input and the feedback clock. Since the output of the charge pump controls the VCO, the output frequency gets periodically disturbed from compensating for the DC offset.
Another non-ideality of the charge pump is a transient glitch. Ideally, when up and down currents are equal, the output control voltage Vc should not change after PFD (phase frequency detector) updating. However, although the overall average voltage does not change, it can cause a transient disturbance. Since this voltage controls the frequency (or phase) of the PLL output, the output frequency will change according to fvco=KVCO*Vc, where KVCO is the gain of the VCO, which is defined as KVCO=d(fout)/d(Vc). A charge pump without a good transient response will have poor spur performance, which presents a problem in communication systems.
It is desirable to have a wide operating range of the charge pump. In silicon wafer processing, due to random manufacturing conditions, devices will have process corners known as typical, slow, and fast, for both NMOS and PMOS devices. For resistors, there is a typical resistor, a low resistor, and a high resistor corners. When integrated circuits (IC) are placed in an application, the supply voltage can vary by a certain percentage. Also, environment temperature can change. Typically, a solid state design needs to pass all potential process, voltage, and temperature (PVT) corners to operate reliably in the field.
For the charge pump, a wide operation range also means a wide tuning range. The tuning range is the possible frequencies that a PLL can cover at all PVT corners. At the PVT corners, the control voltage of PLL needs to adjust to lock to a proper value so that the PLL remains locked. Ideally the control voltage should go from near ground to supply voltage Vdd.
What is needed, therefore, is a charge pump that allows the PLL to operate over a wider range without introducing non-linearity effects.